Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation
A highly efficient, hardware-aware framework using genetic programming to evolve heterogeneous, layer-specific scalar functions from pre-trained weights, eliminating the need for model retraining. It recovers 84.25% Top-1 ImageNet-1K accuracy in only 20 epochs, capturing 91.6% variance (R²) compared to 70.2% for homogeneous baselines, and removes the global reduction bottleneck for efficient ViT deployment on edge devices.
[2605.14047] Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation
[Submitted on 13 May 2026]
Title:Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation
View a PDF of the paper titled Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation, by Kieran Carrigg and 3 other authors
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Abstract:Vision Transformers (ViTs) achieve state-of-the-art performance on challenging vision tasks, but their deployment on edge devices is severely hindered by the computational complexity and global reduction bottleneck imposed by layer normalization. Recent methods attempt to bypass this by replacing normalization layers with hardware-friendly scalar approximations. However, these homogeneous replacements do not optimally fit to all layers' behaviour and rely on expensive model retraining. In this work, we propose a highly efficient, hardware-aware framework that utilizes genetic programming (GP) to evolve heterogeneous, layer-specific scalar functions directly from pre-trained weights. Coupled with a novel post-training re-alignment strategy, our approach eliminates the need to retrain models from scratch entirely. Our evolved expressions accurately approximate the target normalization behaviours, capturing $91.6\%$ of the variance ($R^2$) compared to only $70.2\%$ for homogeneous baselines, allowing our modified architecture to recover $84.25\%$ Top-1 ImageNet-1K accuracy in only 20 epochs. By preserving this performance while eliminating the global reduction bottleneck, our approach establishes a highly favourable trade-off between arithmetic complexity and off-chip memory traffic, removing a primary barrier to the efficient deployment of ViTs on edge accelerators.
Comments: 18 pages, 7 figures
Subjects:
Computer Vision and Pattern Recognition (cs.CV); Hardware Architecture (cs.AR)
Cite as: arXiv:2605.14047 [cs.CV]
(or arXiv:2605.14047v1 [cs.CV] for this version)
https://doi.org/10.48550/arXiv.2605.14047
arXiv-issued DOI via DataCite (pending registration)
Submission history
From: Kieran Carrigg [view email] [v1] Wed, 13 May 2026 19:08:55 UTC (1,057 KB)
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