The invisible fabric of AI: chips aren't a US-China war, but a 30-country chain

By Carlos Ortet · From 498A, a European AI lab · May 23, 2026

Illustration: Tara Jacoby.

Every AI chip that trains a model at OpenAI, Anthropic or Mistral needs a set of mirrors polished in a German factory, a chemical resin mixed in a Japanese laboratory, and a packaging building in Taiwan whose waiting list runs past a year. Without any one of these three elements, the chip does not exist. None of them is American or Chinese.

Almost nobody describes this international fabric: the supply chain of an advanced processor depends on the coordinated work of more than thirty countries. Not two. What are they really talking about, then, when they talk about the “chip war”? The narrative that frames artificial intelligence as an arm-wrestle between the United States and China hides the real map, which is far more interesting: a global fabric of crossed technical monopolies in which no one controls the complete system and where any attempt to break it ends up striking back at the breaker.

It is worth understanding that map for two reasons. First, because it explains why the fragmentation many analysts take for granted is, in fact, physically impossible without costs no government is willing to pay. Second, because Europe is already inside that fabric as a critical node, and almost no one on the continent appears to have noticed.

And there is a third reason, less technical and more political. If we accept the narrative in which Europe has no voice, no vote and no leverage in AI, we resign ourselves to being irrelevant when we are not. We have the capability —and, it bears saying, also the responsibility— to play a key role in how artificial intelligence evolves over the next ten years. Resigning before starting is a choice, and it is not the one the real map allows us to make.

What you need to know

A single advanced chip fab depends on materials, equipment, software and know-how from more than 30 countries. The “US-China war” hides this structural interdependence.

The real bottleneck of global AI is not the chip, it is CoWoS packaging: three TSMC buildings in Taiwan with waiting lists of 52 to 78 weeks.

The Pentagon, OpenAI and Mistral all depend on the same German industrial optician: Carl Zeiss SMT is the sole world supplier of EUV mirrors.

Europe already holds five or six technical monopolies in the chain. If it played as a bloc, it would be indispensable. The right strategy is not “self-sufficiency”; it is indispensability.

ASML bought 11% of Mistral for €1.3 billion in September 2025. European compute + IP integration is already happening, quietly.

The original Chips Act failed in part — Intel Magdeburg was cancelled in July 2025 — but Chips Act 2.0 (Q2 2027) could give the Commission direct authority to invest in fabs.

Trump rescinded the AI Diffusion Rule in May 2025 because it treated NATO allies as Tier 2. The US government itself acknowledged that its own policy was tearing the allied fabric apart.

The dominant narrative

The world’s chip manufacturing system rests on eight linked dependencies. Before a single atom of silicon is touched, the chip is designed in EDA software (Electronic Design Automation), where three companies concentrate over 90% of the market: two American — Synopsys and Cadence — with around 30% each, and Siemens EDA with about 13%. Every chip designed on Earth — any Apple processor, any custom ASIC, any Nvidia GPU — flows through one of these three software packages. The reason is brutal: mathematically proving that a chip with billions of transistors will work before manufacturing it is not something you do anywhere. A respin — redoing the design because something failed — costs between $50 and $100 million on an advanced node, and more than 60% of first-time designs require one. Synopsys and Cadence are wealthy precisely because they charge to avoid the inevitable.

Second dependency: silicon wafers. The 300 mm discs that serve as foundation. They must be produced at 99.999999% purity. Only two companies make them at industrial scale: Shin-Etsu Chemical and Sumco, both Japanese. Together they control roughly half of the critical 300 mm segment. Their advantage is inherited: decades of precision manufacturing dating back to the 1970s, chemical and equipment suppliers clustered in the same industrial region, and a culture of lot-to-lot consistency that no one has replicated.

Third dependency: photoresist, the chemical “ink” applied to the wafer so light can draw the circuit. For EUV (extreme ultraviolet lithography), the same brutal 99.999999% purity, but in a liquid compound. What the popular telling suggests — that Japan has “100% of the monopoly” — is overstated: it is in fact a Japanese-Korean oligopoly where JSR holds around 22% and the top five makers account for about 50% of the market. The nuance does not change the conclusion: dependency is concentrated in a single region, and in 2019 Japan restricted exports to South Korea, threatening Samsung and SK Hynix. The precedent is on the record.

Fourth: process gases. Here Ukraine enters: before 2022 it produced roughly 50% of the world’s neon and supplied up to 90% of the neon consumed by the US semiconductor industry. The reason is historical. The USSR built large-scale steel mills to feed its military complex, and those mills captured neon as a by-product. Two Ukrainian companies inherited and perfected the purification. When the Russian invasion of February 2022 paralysed those plants, neon prices spiked. China stepped in as a replacement and POSCO in South Korea announced expansion, but the market is still rebalancing.

Fifth, the most famous: ASML. The Dutch company headquartered in Veldhoven is the only firm in the world that builds EUV lithography machines. 100% of the market. Each machine costs about $180 million in its current low-NA generation and the new High-NA — already installed at Intel, Samsung, SK Hynix and IMEC — runs around $380 million. Each unit contains over 100,000 components; ASML makes 15%, the rest comes from more than 5,000 suppliers. The two critical ones are German and American: Carl Zeiss SMT, sole world supplier of EUV mirrors, and Cymer, in California, sole maker of the laser source that generates EUV light. ASML acquired Cymer in 2013, but its technology remains US-origin. That is the legal lever by which Washington can prevent ASML from selling to China: the Foreign Direct Product Rule. That is also why China cannot build top-tier AI chip fabs.

Sixth: etch, deposition, inspection. After each lithography step, you carve, deposit and verify. The United States dominates here through Lam Research and Applied Materials — together around 60% of dry etch — and through KLA, the world reference in process inspection. Tokyo Electron, Japanese, leads thermal processing and, more importantly, controls 100% of the coaters and developers that accompany every EUV scanner. Without this quality-control layer, no fab knows whether what it is producing actually works. In April 2026, the US government extended its China export bans to this equipment.

Seventh: photomasks and pellicles. The templates that lithography projects. Canon and Shin-Etsu supply the dust-protection membranes, but one Japanese company — Lasertec — controls 100% of the world market for actinic mask inspection at 5 nm or below. A 1,460-employee firm with technical veto power over the entire advanced production of the planet.

Eighth and most visible: the foundries. TSMC in Taiwan reached a record 70.2% of the global foundry market in Q2 2025. Samsung sits at 7.3%, down from 12% a year earlier, with yields near 50% on 3 nm GAA versus TSMC’s 90%. SMIC in China is capable but blocked by export controls. When Morris Chang founded TSMC in 1987, he bet that chip companies would prefer not to own fabs. He was right. Apple designs chips. Nvidia designs chips. Neither builds them.

The complete semiconductor value chain. Source: RedChalk Group.

This is the map that appears in every serious analysis. It is what Council on Foreign Relations analysts repeat, what Bloomberg explainers illustrate, what Morris Chang cites in interviews. And yet, without being an expert, I get the impression that it is incomplete.

The half that nobody tells

The 5 physical stages of an AI chip: design, lithography, wafer, packaging, test. The real bottleneck is CoWoS packaging, not the chip itself. Infographic: GEOradar / 498A.

Half the chain is missing. The half that actually determines how many AI models the world can train each quarter.

Nvidia’s real bottleneck is not the chip. It is the packaging. Every H100, H200 and B200 GPU delivered for AI training passes through a TSMC technique called CoWoS (Chip-on-Wafer-on-Substrate). At the end of 2023, TSMC produced 13,000 monthly wafers of CoWoS. The target for the end of 2026 is 120,000 to 130,000: a tenfold capacity increase in three years. Even so, it is not enough. Nvidia has reserved more than 50% of all CoWoS capacity for 2026. The three fabs TSMC dedicates to this — AP3, AP5 and AP6 — are saturated, with lead times of 52 to 78 weeks. The consequence is elegant: even if you have a wafer slot in N3, the chip does not ship without CoWoS. The real bottleneck of global AI is three packaging buildings in Taiwan. AMD lives a parallel story, worse: its MI300X uses a different technique, SoIC, with significantly more limited capacity.

52-78

weeks of waiting time for CoWoS at TSMC’s three dedicated fabs (AP3, AP5, AP6), all saturated.

>50%

of total 2026 CoWoS capacity already reserved by Nvidia. The rest is shared between AMD, Google, AWS and Broadcom.

485 → 950

TWh of electricity that global data centres will consume between 2025 and 2030, per the IEA. The US and China generate 80% of the growth.

€1.3B

that ASML invested in Mistral in September 2025, securing 11% of the most promising European AI lab.

The second invisible bottleneck is HBM memory (High Bandwidth Memory). Every modern AI GPU carries stacks of memory chips piled vertically with brutal bandwidth. The market grew from $17 billion in 2024 to about $34 billion in 2025: it doubled in twelve months. Micron’s projections put it at $100 billion in 2028. Something else happened almost no one is underlining: in Q3 2025, SK Hynix held 57% of the HBM market, Samsung 22% and Micron 21%. SK Hynix became the world’s number one in DRAM for the first time, overtaking Samsung for the first time since 1983. AI has just reordered four decades of Korean memory hierarchy.

The third invisible bottleneck is software: CUDA. Nvidia controls over 90% of the data centre GPU market for AI, but the real moat is not silicon.

In 2006 Nvidia launched CUDA, a platform that lets programmers use GPU power for complex mathematical computations (essential for AI). They have been refining it for nineteen years, and that time has hardened into three layers of lock-in no rival has matched:

— cuDNN, cuBLAS, NCCL. Hyper-specialised libraries — pre-built tools — that make AI run at the speed of light on Nvidia hardware. Every frequent mathematical operation in deep learning is already optimised to the limit inside these libraries.

— Integration with PyTorch and TensorFlow. The two “languages” data scientists use worldwide are designed to integrate flawlessly with Nvidia from day one. Use another brand and programming becomes a nightmare of errors and patches.

— Documentation and community. Nineteen years of manuals, tutorials, forums and university courses. Migrating off CUDA is not just switching GPUs: it is retraining an entire generation of engineers.

AMD ROCm closed the hardware gap in 2025, but the software maturity gap is still there. Intel oneAPI, the UXL Foundation backed by ARM, Samsung and Qualcomm, and emerging proposals like MLX, Modular Mojo, Triton and JAX all try to erode the lock-in. But as of May 2026, none has produced a material shift. The moat is cultural before it is technical.

The fou

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