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Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey

Summary

This survey by Hamza Kheddar reviews more than 100 studies on implementing reinforcement learning on FPGA and integrated-circuit platforms, organizing the literature by RL family, abstraction level, hardware realization strategy, and application domain, while comparing resource use, latency, throughput, power, and performance gains and outlining recurring architectural patterns, practical limits, and open research directions.

SourcearXiv Machine LearningAuthor: Hamza Kheddar
Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey
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[Submitted on 20 Oct 2026]

Title:Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey

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Abstract:Reinforcement learning (RL) enables adaptive and autonomous decision-making in embedded, edge, and heterogeneous computing systems. Field-programmable gate arrays (FPGAs) and integrated circuits (ICs) offer low latency, energy efficiency, and architectural flexibility for RL deployment, while introducing challenges in resource constraints, implementation complexity, and hardware-algorithm co-design. This review surveys more than 100 studies on RL implementations across FPGA and IC platforms, emphasizing architectures, implementation strategies, performance evaluation, and applications. The literature is organized by RL family, including model-based Markov decision processes, classical value-based methods, deep RL, actor-critic, policy-gradient, and multi-agent approaches. We further classify studies by abstraction level, hardware realization strategy, and application domain, examining how RL algorithms map onto reconfigurable and fixed hardware. Unlike surveys restricted to particular algorithms or platforms, this work provides a unified analysis of FPGA and IC implementations, covering acceleration, reconfigurable architectures, energy-aware control, and system-level optimization. Comparative assessments consider resource utilization, latency, throughput, power consumption, and reported performance gains. Finally, we identify recurring architectural patterns, practical limitations, open challenges, and research directions for efficient RL-driven hardware systems. The survey offers a consolidated reference for researchers developing and evaluating RL solutions on specialized hardware.

Subjects:

Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Performance (cs.PF); Robotics (cs.RO); Systems and Control (eess.SY)

Cite as: arXiv:2610.28699 [cs.LG]

(or arXiv:2610.28699v1 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2610.28699

arXiv-issued DOI via DataCite (pending registration)

Journal reference: Journal of Systems Architecture, 2026

Related DOI:

https://doi.org/10.1016/j.sysarc.2026.103874

DOI(s) linking to related resources

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From: Hamza Kheddar [view email] [v1] Tue, 20 Oct 2026 11:15:34 UTC (1,201 KB)

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Key points

  • The survey covers over 100 studies on RL implementations across FPGA and IC platforms.
  • Literature is organized by RL family, abstraction level, hardware realization strategy, and application domain.
  • Comparative assessments consider resource utilization, latency, throughput, power consumption, and reported performance gains.
  • The paper identifies recurring architectural patterns, practical limitations, open challenges, and research directions.

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