[2606.19347] How LLMs Fail and Generalize in RTL Coding for Hardware Design?
[Submitted on 26 Apr 2026]
Title:How LLMs Fail and Generalize in RTL Coding for Hardware Design?
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Abstract:Translating sequential programming priors into the parallel temporal logic of hardware design remains a crucial bottleneck for large language models(LLM). To investigate this, we introduce a new error taxonomy grounded in problem solvability, inspired by cognitive theory. Our taxonomy categorizes failures into syntactic, semantic, solvable functional, and unsolvable functional types. Evaluations reveal a strict empirical ceiling on the VerilogEval benchmark, as frontier models plateau at a 90.8% initial pass rate. These plateaus are defined by unsolvable functional errors, exposing persistent knowledge gaps immune to test time compute scaling. Furthermore, we expose a striking surface convergence gap: optimization readily eliminates syntax errors but concurrently exacerbates deeper functional failures. Our findings demonstrate that alignment techniques merely teach models to compile. While repeated sampling strategies can patch solvable errors, register-transfer level(RTL) coding capacity remains strictly bounded by pretraining knowledge. Addressing challenges in the current LLM based hardware generation pipeline requires more studies in model reasoning rather than alignment interventions.
Comments: Preview, under submission for EMNLP 2026
Subjects:
Computation and Language (cs.CL); Artificial Intelligence (cs.AI); Programming Languages (cs.PL)
Cite as: arXiv:2606.19347 [cs.CL]
(or arXiv:2606.19347v1 [cs.CL] for this version)
https://doi.org/10.48550/arXiv.2606.19347
arXiv-issued DOI via DataCite
Submission history
From: Guan-Ting Liu [view email] [v1] Sun, 26 Apr 2026 14:34:49 UTC (485 KB)
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