Hardware Mechanisms to Dynamically Throttle AI Performance
As AI models integrate into critical systems, existing software safeguards may be bypassed. Researchers propose microarchitecture knobs that dynamically control GPU memory subsystem resources (L2 cache size, latency, bandwidth, shared memory port access rate) to limit AI performance at runtime, achieving up to 80% performance reduction with negligible cost.
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[Submitted on 20 Jul 2026]
Title:Hardware Mechanisms to Dynamically Throttle AI Performance
View a PDF of the paper titled Hardware Mechanisms to Dynamically Throttle AI Performance, by Haiyue Ma and 3 other authors
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Abstract:As more capable AI models are increasingly integrated into critical computer systems, the lack of control over AI intent motivates safety mechanisms. Existing software safeguards impose only behavioral constraints that can potentially be bypassed by sufficiently intelligent models. While hardware-level safety enforcement has been recognized as an essential last line of defense, few mechanisms have been proposed beyond policy regulations on unauthorized accesses or coarse full-chip shutdown. What is missing is a fine-grained, dynamic intervention mechanism at the architecture level.
In this paper, we introduce a set of microarchitecture knobs which dynamically control the available hardware resources to limit AI performance at runtime. We evaluate candidate knobs spanning the GPU memory subsystem, across capacity, bandwidth, latency and frequency dimensions, and narrow down to four strong candidates: L2 size, L2 latency, L2 bandwidth, and shared memory port access rate. To minimize new logic and extra design cost, we build all four mechanisms from well-established microarchitectural primitives: cache way masking, credit-based rate limiting, latency insertion, and bank arbitration. We show that these knobs achieve high performance sensitivity (up to 80% performance cut at 1/8 resource availability), negligible implementation cost (
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